Non-volatile semiconductor storage device

ABSTRACT

Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

More than one reissue application has been filed for the reissue of U.S.Pat. No. 7,933,151. The reissue applications are application Ser. No.13/870,676 (grandparent application), application Ser. No. 14/026,844(parent application and divisional of Ser. No. 13/870,676), and thepresent continuation application. The present application claims benefitof priority under 35 U.S.C. § 120 of application Ser. No. 14/026,844.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2008-291779, filed on Nov. 14,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrically rewritable non-volatilesemiconductor storage device.

2. Description of the Related Art

Conventionally, LSIs are formed by integration of devices in atwo-dimensional plane on the silicon substrate. Although the dimensionfor each device must be reduced (refined) to increase memory storagecapacity, recent years are facing challenges in such refinement from theviewpoint of cost and technology. Such refinement requires furtherimprovements in photolithography technology. However, in currentlyavailable ArF immersion lithography technology, for example, theresolution limit has been reached around the 40 nm design rule and soEUV exposure devices have to be introduced for further refinement.However, the EUV exposure devices are expensive and infeasible in viewof the costs. In addition, if such refinement is accomplished, it isassumed that physical improvement limit, such as in breakdown voltagebetween devices, would be reached unless driving voltage can be scaled.That is, it is likely that difficulties would be encountered in deviceoperation itself.

Therefore, a large number of semiconductor storage devices have beenproposed recently where memory cells are arranged in a three-dimensionalmanner to achieve improved integration of memory devices (see, PatentDocument 1: Japanese Patent Laid-Open No. 2007-266143; Patent Document2: U.S. Pat. No. 5,599,724; and Patent Document 3: U.S. Pat. No.5,707,885).

One of the conventional semiconductor storage devices where memory cellsare arranged in a three-dimensional manner uses transistors with acylinder-type structure (see, Patent Documents 1 to 3). Thosesemiconductor storage devices using transistors with the cylinder-typestructure are provided with multiple laminated conductive layerscorresponding to gate electrodes and pillar-like columnarsemiconductors. Each of the columnar semiconductors serves as a channel(body) part of each of the transistors. Memory gate insulation layersthat can accumulate electric charges are provided around the columnarsemiconductors. Such a configuration including laminated conductivelayers, columnar semiconductors, and memory gate insulation layers isreferred to as a “memory string”.

Regarding the semiconductor storage devices with the above-mentionedmemory strings, there is a need for reading data from a selected memorystring in a more precise manner.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a non-volatilesemiconductor storage device comprising: a plurality of memory strings,each having a plurality of electrically rewritable memory cellsconnected in series; and a plurality of first selection transistorsconnected to one ends of the respective memory strings, each of thememory strings comprising: a first semiconductor layer including acolumnar portion extending in a direction perpendicular to a substrate;a first electric charge storage layer formed to surround a side surfaceof the columnar portion; and a first conductive layer formed to surrounda side surface of the columnar portion as well as the first electriccharge storage layer, the first conductive layer functioning as acontrol electrode of a respective one of the memory cells, each of thefirst selection transistors comprising: a second semiconductor layerextending upward from a top surface of the columnar portion; a secondelectric charge storage layer formed to surround a side surface of thesecond semiconductor layer; and a second conductive layer formed tosurround a side surface of the second semiconductor layer as well as thesecond electric charge storage layer, the second conductive layerfunctioning as a control electrode of a respective one of the firstselection transistors, the non-volatile semiconductor storage devicefurther comprising a control circuit configured to cause, prior toreading data from a selected one of the memory strings, electric chargesto be accumulated in the second electric charge storage layer of one ofthe first selection transistors connected to an unselected one of thememory strings.

Another aspect of the present invention provides a non-volatilesemiconductor storage device comprising: a plurality of memory strings,each having a plurality of electrically rewritable memory cellsconnected in series; and a plurality of first selection transistorsconnected to one ends of the respective memory strings, each of thememory strings comprising: a first semiconductor layer including acolumnar portion extending in a direction perpendicular to a substrate;a first electric charge storage layer formed to surround a side surfaceof the columnar portion; and a first conductive layer formed to surrounda side surface of the columnar portion as well as the first electriccharge storage layer, the first conductive layer functioning as acontrol electrode of a respective one of the memory cells, each of thefirst selection transistors comprising: a second semiconductor layerextending downward from a bottom surface of the columnar portion; asecond electric charge storage layer formed to surround a side surfaceof the second semiconductor layer; and a second conductive layer formedto surround a side surface of the second semiconductor layer as well asthe second electric charge storage layer, the second conductive layerfunctioning as a control electrode of a respective one of the firstselection transistors, the non-volatile semiconductor storage devicefurther comprising a control circuit configured to cause, prior toreading data from a selected one of the memory strings, electric chargesto be accumulated in the second electric charge storage layer of one ofthe first selection transistors connected to an unselected one of thememory strings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a non-volatile semiconductor storage device100 according to a first embodiment of the present invention;

FIG. 2 is a schematic perspective view of a memory cell array 11;

FIG. 3 is an enlarged view of FIG. 2;

FIG. 4 is a cross-sectional view of FIG. 3;

FIG. 5 is a circuit diagram of the non-volatile semiconductor storagedevice 100;

FIG. 6 is a timing chart illustrating a write operation of thenon-volatile semiconductor storage device 100 according to the firstembodiment;

FIG. 7 is a timing chart illustrating a read operation of thenon-volatile semiconductor storage device 100 according to the firstembodiment;

FIG. 8 is a timing chart illustrating an erase operation of thenon-volatile semiconductor storage device 100 according to the firstembodiment;

FIG. 9 is a flowchart illustrating an operation to be performed beforeand after the read operation in the non-volatile semiconductor storagedevice 100 according to the first embodiment;

FIG. 10 illustrates “Case 1” of the pre-programming at step S101;

FIG. 11 illustrates “Case 2” of the pre-programming at step S101;

FIG. 12 illustrates “Case 3” of the pre-programming at step S101;

FIG. 13 is a timing chart illustrating the pre-programming operation(step S101);

FIG. 14 is a timing chart illustrating the pre-programming eraseoperation (step S103);

FIG. 15 is a cross-sectional view of one memory block MBa according to asecond embodiment;

FIG. 16 is a flowchart illustrating an operation to be performed beforeand after the read operation in the non-volatile semiconductor storagedevice according to the second embodiment;

FIG. 17 illustrates “Case 4” of the pre-programming at step S201;

FIG. 18 illustrates “Case 5” of the pre-programming at step S201;

FIG. 19 illustrates “Case 6” of the pre-programming at step S201;

FIG. 20 is a timing chart illustrating the pre-programming operation(step S201);

FIG. 21 is a timing chart illustrating the pre-programming eraseoperation (step S203);

FIG. 22 is a cross-sectional view of one memory block MBb according tothe third embodiment;

FIG. 23 is a circuit diagram of memory blocks MBc in a non-volatilesemiconductor storage device according to a fourth embodiment;

FIG. 24 is a schematic perspective view of one memory block MBc in thenon-volatile semiconductor storage device of the fourth embodiment; and

FIG. 25 is an enlarged cross-sectional view of a part of FIG. 24.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of anon-volatile semiconductor storage device according tothe present invention will now be described below with reference to theaccompanying drawings.

First Embodiment

Configuration of Non-Volatile Semiconductor Storage Device 100 in FirstEmbodiment

Referring first to FIG. 1, a configuration of a non-volatilesemiconductor storage device 100 according to a first embodiment will bedescribed below. FIG. 1 is a block diagram of the non-volatilesemiconductor storage device 100 according to the first embodiment ofthe present invention.

As illustrated in FIG. 1, the non-volatile semiconductor storage device100 of the first embodiment comprises: a memory cell array 11; rowdecoders 12 and 13; a sense amplifier 14; a column decoder 15; and acontrol signal generation unit (high-voltage generation unit) 16.

The memory cell array 11 has memory transistors MTr for electricallystoring data. The row decoders 12 and 13 decode captured block addresssignals and gate address signals. The row decoders 12 and 13 alsocontrol the memory cell array 11. The sense amplifier 14 reads data fromthe memory cell array 11. The column decoder 15 decodes column addresssignals and controls the sense amplifier 14. The control signalgeneration unit 16 boosts a reference voltage to generate a high voltagethat is required at the time of write and erase operations. Furthermore,The control signal generation unit 16 generates a control signal tocontrol the row decoders 12 and 13, the sense amplifier 14, and thecolumn decoder 15.

Referring now to FIGS. 2 to 4, a lamination structure and a circuitconfiguration of the memory cell array 11 will be described below. FIG.2 is a schematic perspective view of a memory cell array 11. FIG. 3 isan enlarged view of FIG. 2. FIG. 4 is a cross-sectional view of FIG. 3.Wherein, the row direction represents a direction orthogonal to thelamination direction and the column direction represents anotherorthogonal to the lamination direction and the row direction. Note thatinterlayer insulation layers provided between wirings are omitted fromFIG. 3.

As illustrated in FIG. 2, the memory cell array 11 has a plurality ofmemory blocks MB. The memory blocks MB are arranged in the columndirection on a semiconductor substrate Ba (not illustrated). In otherwords, one memory block MB is formed for each certain region on thesemiconductor substrate Ba.

As illustrated in FIG. 2, each memory block MB comprises a plurality ofmemory strings MS, source-side selection transistors SSTr, anddrain-side selection transistors SDTr. Each memory string MS includesmemory transistors MTr1 to MTr4 connected in series. Each drain-sideselection transistor SDTr is connected to one end (a memory transistorMTr4) of a respective memory string MS. Each source-side selectiontransistor SSTr is connected to the other end (a memory transistor MTr1)of a respective memory string MS. For example, each memory block MB hasmultiple rows and four columns of memory strings MS provided therein.Note that each memory string MS may include four or more memorytransistors. In addition, four or more columns of memory strings MS maybe provided in each memory block MB.

As illustrated in FIG. 2, in each memory block MB, the control gates ofthe memory transistors MTr1 arranged in a matrix form are commonlyconnected to a word line WL1. Similarly, the control gates of the memorytransistors MTr2 are commonly connected to a word line WL2. The controlgates of the memory transistors MTr3 are commonly connected to a wordline WL3. The control gates of the memory transistors MTr4 are commonlyconnected to a word line WL4. The word lines WL1 to WL4 are controlledby independent signals.

As illustrated in FIG. 2, in each memory block MB, the control gates ofthe drain-side selection transistors SDTr arranged in the row directionare commonly connected to a drain-side selection gate line SGD. Eachdrain-side selection gate line SGD is formed to extend in the rowdirection across a plurality of memory blocks MB. A plurality ofdrain-side selection gate lines SGD, which are provided in the columndirection, are controlled by independent signals. In addition, the otherends of the drain-side selection transistors SDTr arranged in the columndirection are commonly connected to a bit line BL. Each bit line BL isformed to extend in the column direction across the memory blocks MB. Aplurality of bit lines BL, which are provided in the row direction, arecontrolled by independent signals.

As illustrated in FIG. 2, in each memory block MB, the control gates ofthe source-side selection transistors SSTr arranged in the row directionare commonly connected to a source-side selection gate line SGS. Eachsource-side selection gate line SGS is formed to extend in the rowdirection across a plurality of memory blocks MB. A plurality ofsource-side selection gate lines SGS, which are provided in the columndirection, are controlled by independent signals. In addition, the otherends of the source-side selection transistors SSTr arranged in thecolumn direction are commonly connected to a source line SL.

The circuit configuration of the memory blocks MB as described above isachieved by the lamination structure illustrated in FIGS. 3 and 4. Eachmemory block MB has a source-side selection transistor layer 20, amemory transistor layer 30, and a drain-side selection transistor layer40 that are sequentially laminated on the semiconductor substrate Ba.

The source-side selection transistor layer 20 is a layer that functionsas source-side selection transistors SSTr. The memory transistor layer30 is a layer that functions as memory strings MS (memory transistorsMTr1 to MTr4). The drain-side selection transistor layer 40 is a layerthat functions as drain-side selection transistors SDTr.

As illustrated in FIGS. 3 and 4, the source-side selection transistorlayer 20 has source-side first insulation layers 21, source-sideconductive layers 22, and source-side second insulation layers 23 thatare sequentially formed on the semiconductor substrate Ba. Eachsource-side conductive layer 22 is formed to extend in the rowdirection. Note that an interlayer insulation layer 24 is formed on thesidewall of each source-side conductive layer 22.

The source-side first insulation layers 21 and the source-side secondinsulation layers 23 are composed of, e.g., silicon oxide (SiO₂) orsilicon nitride (SiN). The source-side conductive layers 22 are composedof, e.g., polysilicon (p-Si).

As illustrated in FIG. 4, the source-side selection transistor layer 20also has source-side holes 25 that are formed to penetrate thesource-side first insulation layers 21, the source-side conductivelayers 22, and the source-side second insulation layers 23. Thesource-side holes 25 are formed in a matrix form in the row and columndirections.

Furthermore, as illustrated in FIG. 4, the source-side selectiontransistor layer 20 has source-side gate insulation layers 26 andsource-side columnar semiconductor layers 27 that are sequentiallyformed on the sidewalls of the source-side holes 25. The source-sidegate insulation layers 26 are formed with a certain thickness on thesidewalls of the source-side holes 25. The source-side columnarsemiconductor layers 27 are formed to fill up the source-side holes 25.Each source-side columnar semiconductor layer 27 is formed in a columnarshape extending in the lamination direction. The top surfaces of thesource-side columnar semiconductor layers 27 are formed in contact withthe bottom surfaces of respective memory columnar semiconductor layers35 described below. The source-side columnar semiconductor layers 27 areformed on a diffusion layer Ba1 on the semiconductor substrate Ba. Thediffusion layer Ba1 functions as a source line SL.

The source-side gate insulation layers 26 are composed of, e.g., siliconoxide (SiO₂). The source-side columnar semiconductor layers 27 arecomposed of, e.g., polysilicon (p-Si).

According to the configuration of the source-side selection transistorlayer 20 as mentioned above, the source-side conductive layers 22function as the control gates of the source-side selection transistorsSSTr. The source-side conductive layers 22 also function as source-sideselection gate lines SGS.

As illustrated in FIGS. 3 and 4, the memory transistor layer 30 hasfirst to fifth insulation layers between word lines 31a to 31e and firstto fourth word-line conductive layers 32a to 32d that are sequentiallylaminated on the source-side selection transistor layer 20. The first tofourth word-line conductive layers 32a to 32d are formed to expand in atwo-dimensional manner (in a plate-like form) in the row and columndirections. The first to fourth word-line conductive layers 32a to 32dare separated for each memory block MB.

The first to fifth insulation layers between word lines 31a to 31e arecomposed of, e.g., silicon oxide (SiO₂). The first to fourth word-lineconductive layers 32a to 32d are composed of, e.g., polysilicon (p-Si).

As illustrated in FIG. 4, the memory transistor layer 30 also has memoryholes 33 that are formed to penetrate the first to fifth insulationlayers between word lines 31a to 31e and the first to fourth word-lineconductive layers 32a to 32d. The memory holes 33 are formed in a matrixform in the row and column directions. The memory holes 33 are formed atpositions matching the source-side holes 25.

Furthermore, as illustrated in FIG. 4, the memory transistor layer 30has block insulation layers 34a, electric charge storage layers 34b,tunnel insulation layers 34c, and memory columnar semiconductor layers35 that are sequentially formed on the sidewalls of the memory holes 33.The block insulation layers 34a are formed with a certain thickness onthe sidewalls of the memory holes 33. The electric charge storage layers34b are formed with a certain thickness on the sidewalls of the blockinsulation layers 34a. The tunnel insulation layers 34c are formed witha certain thickness on the sidewalls of the electric charge storagelayers 34b. The memory columnar semiconductor layers 35 are formed tofill up the memory holes 33. Each memory columnar semiconductor layer 35is formed in a columnar shape extending in the lamination direction. Thebottom surfaces of the memory columnar semiconductor layers 35 areformed in contact with the top surfaces of the respective source-sidecolumnar semiconductor layers 27. In addition, the top surfaces of thememory columnar semiconductor layers 35 are formed in contact with thebottom surfaces of respective drain-side columnar semiconductor layers47 described below.

The block insulation layers 34a and the tunnel insulation layers 34c arecomposed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 34b are composed of, e.g., silicon nitride (SiN). The memorycolumnar semiconductor layers 35 are composed of, e.g., polysilicon(p-Si).

In the configuration of the memory transistor layer 30 as mentionedabove, the first to fourth word-line conductive layers 32a to 32dfunction as the control gates of the memory transistors MTr1 to MTr4.The first to fourth word-line conductive layers 32a to 32d also functionas parts of the word lines WL1 to WL4.

As illustrated in FIGS. 3 and 4, the drain-side selection transistorlayer 40 has drain-side first insulation layers 41, drain-sideconductive layers 42, and drain-side second insulation layers 43 thatare sequentially laminated on the memory transistor layer 30. Thedrain-side conductive layers are formed immediately above where thememory columnar semiconductor layers 35 are formed. The drain-sideconductive layers 42 are formed to extend in the row direction. Notethat interlayer insulation layers 44 are formed on the sidewalls of thedrain-side conductive layers 42.

The drain-side first insulation layers 41 and the drain-side secondinsulation layers 43 are composed of, e.g., silicon oxide (SiO₂) orsilicon nitride (SiN). The drain-side conductive layers 42 are composedof, e.g., polysilicon (p-Si).

As illustrated in FIG. 4, the drain-side selection transistor layer 40also has drain-side holes 45 that are formed to penetrate the drain-sidefirst insulation layers 41, the drain-side conductive layers 42, and thedrain-side second insulation layers 43. The drain-side holes 45 areformed in a matrix form in the row and column directions. The drain-sideholes 45 are formed at positions matching the memory holes 33.

Furthermore, as illustrated in FIG. 4, the drain-side selectiontransistor layer 40 has block insulation layers 46a, electric chargestorage layers 46b, tunnel insulation layers 46c, and the drain-sidecolumnar semiconductor layers 47 that are sequentially formed on thesidewalls of the drain-side holes 45. The block insulation layers 46aare formed with a certain thickness on the sidewalls of the drain-sideholes 45. The electric charge storage layers 46b are formed with acertain thickness on the sidewalls of the block insulation layers 46a.The tunnel insulation layers 46c are formed with a certain thickness onthe sidewalls of the electric charge storage layers 46b. The drain-sidecolumnar semiconductor layers 47 are formed to fill up the drain-sideholes 45. Each drain-side columnar semiconductor layer 47 is formed in acolumnar shape extending in the lamination direction. The bottomsurfaces of the drain-side columnar semiconductor layers 47 are formedin contact with the top surfaces of the memory columnar semiconductorlayers 35. Bit line layers 51 are formed on the top surfaces of thedrain-side columnar semiconductor layers 47. The bit line layers 51 areformed to extend in the column direction at a certain pitch in the rowdirection. The bit line layers 51 function as bit lines BL.

The block insulation layers 46a and the tunnel insulation layers 46c arecomposed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 46b are composed of, e.g., silicon nitride (SiN). The drain-sidecolumnar semiconductor layers 47 are composed of, e.g., polysilicon(p-Si).

In the configuration of the drain-side selection transistor layer 40 asmentioned above, the drain-side conductive layers 42 function as thecontrol gates of the drain-side selection transistors SDTr. Thedrain-side conductive layers 42 also function as parts of drain-sideselection gate lines SGD.

Referring now to FIG. 5, a circuit configuration of the row decoders 12and 13 will be described below. FIG. 5 is a circuit diagram of thenon-volatile semiconductor storage device 100.

As illustrated in FIG. 5, a row decoder 12 has a NAND circuit 121, a NOTcircuit 122, and a voltage conversion circuit 123 for each memory blockMB.

Each NAND circuit 121 receives an address signal Address from thecontrol signal generation unit 16 and outputs it to the NOT circuit 122.The NOT circuit 122 receives the signal from the NAND circuit 121 andoutputs it to the voltage conversion circuit 123. The voltage conversioncircuit 123 converts the voltage of the signal received from the NOTcircuit 122, and then outputs the converted signal to a control gate ofa first transfer transistor 124a described below.

As illustrated in FIG. 5, the row decoder 12 also has a pair of firstand second transfer transistors 124a and 124b for memory strings MSconnected to the same drain-side selection gate line SGD.

One end of the first transfer transistor 124a receives a signal Sg_(SGD)from the control signal generation unit 16. The signal Sg_(SGD) is asignal for driving a particular drain-side selection gate line SGD. Theother end of each first transfer transistor 124a is connected to adrain-side selection gate line SGD. The control gate of each firsttransfer transistor 124a receives a signal from the voltage conversioncircuit 123.

One end of each second transfer transistor 124b receives a signalSg_(SGDOFF) from the control signal generation unit 16. The signalSg_(SGDOFF) is a signal for disabling a drain-side selection gate lineSGD. The other end of each second transfer transistor 124b is connectedto a drain-side selection gate line SGD. The control gate of each secondtransfer transistor 124b receives a signal from the NAND circuit 121.

As illustrated in FIG. 5, the row decoder 12 also has third and fourthtransfer transistors 124c and 124d for each memory block MB.

One ends of the third and fourth transfer transistors 124c and 124dreceive signals Sg_(WL3) and Sg_(WL4), respectively, from the controlsignal generation unit 16. The signals Sg_(WL3) and Sg_(WL4) are signalsfor driving the word lines WL3 and WL4. The other ends of the third andfourth transfer transistors 124c and 124d are connected to the wordlines WL3 and WL4. The control gates of the third and fourth transfertransistors 124c and 124d receive signals from the voltage conversioncircuit 123.

As illustrated in FIG. 5, a row decoder 13 has a NAND circuit 131, a NOTcircuit 132, and a voltage conversion circuit 133 for each memory blockMB.

Each NAND circuit 131 receives an address signal Address from thecontrol signal generation unit 16 and outputs it to the NOT circuit 132.The NOT circuit 132 receives a signal from the NAND circuit 131 andoutputs it to the voltage conversion circuit 133. The voltage conversioncircuit 133 converts the voltage of the signal received from the NOTcircuit 132, and then outputs the converted signal to a control gate ofa first transfer transistor 134a described below.

As illustrated in FIG. 5, the row decoder 13 also has pair of first andsecond transfer transistors 134a and 134b for memory strings MSconnected to the same source-side selection gate line SGS.

One end of the first transfer transistor 134a receives a signal Sg_(SGS)from the control signal generation unit 16. The signal Sg_(SGS) is asignal for driving a particular source-side selection gate line SGS. Theother end of each first transfer transistor 134a is connected to asource-side selection gate line SGS. The control gate of each firsttransfer transistor 134a receives a signal from the voltage conversioncircuit 133.

One end of each second transfer transistor 134b receives a signalSg_(SGSOFF) from the control signal generation unit 16. The signalSg_(SGSOFF) is a signal for disabling a source-side selection gate lineSGS. The other end of each second transfer transistor 134b is connectedto a source-side selection gate line SGS. The control gate of eachsecond transfer transistor 134b receives a signal from the NAND circuit131.

As illustrated in FIG. 5, the row decoder 13 also has third and fourthtransfer transistors 134c and 134d for each memory block MB.

One ends of the third and fourth transfer transistors 134c and 134dreceive signals Sg_(WL1) and Sg_(WL2), respectively, from the controlsignal generation unit 16. The signals Sg_(WL1) and Sg_(WL2) are signalsfor driving the word lines WL1 and WL2. The other ends of the third andfourth transfer transistors 134c and 134d are connected to the wordlines WL1 and WL2. The control gates of the third and fourth transfertransistors 134c and 134d receive signals from the voltage conversioncircuit 133.

Operation of Non-Volatile Semiconductor Storage Device 100 in FirstEmbodiment

An operation of the non-volatile semiconductor storage device 100 of thefirst embodiment will now be described below. Referring first to FIGS. 6to 8, write, read, and erase operations of the non-volatilesemiconductor storage device 100 of the first embodiment will bedescribed below. The operations illustrated in FIGS. 6 to 8 areperformed by the control signal generation unit 16. FIG. 6 is a timingchart illustrating a write operation of the non-volatile semiconductorstorage device 100 according to the first embodiment; FIG. 7 is a timingchart illustrating a read operation thereof; and FIG. 8 is a timingchart illustrating an erase operation thereof.

In this case, it is assumed that the write, read, and erase operationsare performed on one particular memory block MB. The word lines WL1 toWL4 are denoted by “word lines WL”. One of the word lines WL1 to WL4that is selected for write, read, or erase operations is denoted by a“selected word line WL (sel)”. On the other hand, one of the word linesWL1 to WL4 that is not selected for such operations is denoted by an“unselected word line WL (n-sel)”. One of the drain-side selection gatelines SGD that is selected for write, read, or erase operations isdenoted by a “selected drain-side selection gate line SGD (sel)”. On thecontrary, one of the drain-side selection gate lines SGD that is notselected for such operations is denoted by an “unselected drain-sideselection gate line SGD (n-sel)”. One of the source-side selection gatelines SGS that is selected for write, read, or erase operations isdenoted by a “selected source-side selection gate line SGS (sel)”.Meanwhile, one of the source-side selection gate lines SGS that is notselected for such operations is denoted by an “unselected source-sideselection gate line SGS (n-sel)”.

Furthermore, one of the memory blocks MB that is selected for write,read, or erase operations is denoted by a “selected memory block MB(sel)”. On the other hand, one of the memory blocks MB that is notselected for such operations is denoted by an “unselected memory blockMB (n-sel)”. One of the memory strings MS that is selected for write,read, or erase operations is denoted by a “selected memory string MS(sel)”. On the contrary, one of the memory strings MS that is notselected for such operations is denoted by an “unselected memory stringMS (n-sel)”. One of the drain-side selection transistors SDTr that isselected for write, read, or erase operations is denoted by a “selecteddrain-side selection transistor SDTr (sel)”. Meanwhile, one of thedrain-side selection transistors SDTr that is not selected for suchoperations is denoted by an “unselected drain-side selection transistorSDTr (n-sel)”. One of the source-side selection transistors SSTr that isselected for write, read, or erase operations is denoted by a “selectedsource-side selection transistor SSTr (sel)”. In contrast, one of thesource-side selection transistors SSTr that is not selected for suchoperations is denoted by an “unselected source-side selection transistorSSTr (n-sel)”.

In write operation, as illustrated in FIG. 6, the source line SL isinitially set at a voltage Vdd, while the others set at a ground voltageVss. Then, in writing “1” at time t11, the bit line BL is boosted to thevoltage Vdd. Alternatively, in writing “0” at time t11, the bit line BLis maintained at the ground voltage Vss. In addition, at time t11, aselected word line WL (sel) and unselected word lines WL (n-sel) areboosted to the voltage Vdd. Furthermore, at time tll, a selecteddrain-side selection gate line SGD (sel) is boosted to a voltage Vsg.The voltage Vdd is, e.g., on the order of 3V to 4V. The voltage Vsg is,e.g., on the order of 4V. Note that unselected drain-side selection gatelines SGD (n-sel) and unselected source-side selection gate lines SGS(n-sel) are set at the ground voltage Vss. In addition, the word linesWL in unselected blocks MB (n-sel) are set in a floating state.

Subsequently, at time t12, the selected drain-side selection gate lineSGD (sel) is dropped to the voltage Vdd. Then, at time t13, the selectedword line WL (sel) and the unselected word lines WL (n-sel) are boostedto a voltage Vpass. Subsequently, at time t14, the selected word line WL(sel) is boosted to a voltage Vpgm. The voltage Vpass is, e.g., 10V. Thevoltage Vpgm is, e.g., 18V.

Then, at time t15, the selected word line WL (sel), the unselected wordlines WL (n-sel), and the selected drain-side selection gate line SGD(sel) are dropped to the ground voltage Vss.

Through this operation, electric charges are accumulated in the controlgate of the memory transistor MTr in a selected memory string MS (sel)that is connected to the selected word line WL (sel). As a result, datais written to the memory transistor MTr.

In read operation, as illustrated in FIG. 7, the bit line BL, the sourceline SL, the selected word line WL (sel), the unselected word lines(n-sel), the selected drain-side selection gate line SGD (sel), and theselected source-side selection gate line SGS (sel) are initially set atthe ground voltage Vss. Note that the unselected drain-side selectiongate lines SGD (n-sel) and the unselected source-side selection gatelines SGS (n-sel) are set at the ground voltage Vss. Each word line WLin an unselected memory block MB (n-sel) is set in a floating state.

Then, at time t21, the bit line BL is boosted to a voltage Vpre. Thevoltage Vpre is, e.g., on the order of 1V. In addition, at time t21, theunselected word lines WL (n-sel) are boosted to a voltage Vread. Thevoltage Vread is, e.g., on the order of 4V. In addition, at time t21,the selected drain-side selection gate line SGD (sel) is boosted to thevoltage Vsg. Then, at time t22, the selected source-side selection gateline SGS (sel) is boosted to the voltage Vsg.

Subsequently, at time t23, the unselected word lines WL (n-sel), theselected drain-side selection gate line SGD (sel), and the selectedsource-side selection gate line SGS (sel) are dropped to the groundvoltage Vss.

Through this operation, such current is detected that flows from the bitline BL through the selected memory string MS (sel) into the source lineSL (from one end to the other of the memory string MS). Then, data isread through the comparison of the magnitude (large or small) of thedetected current.

In erase operation, as illustrated in FIG. 8, the source line SL, theword line WL, the selected drain-side selection gate line SGD (sel), andthe selected source-side selection gate line SGS (sel) are initially setat the ground voltage Vss. Note that the bit line BL is set in afloating state. In addition, the unselected drain-side selection gatelines SGD (n-sel) and the unselected source-side selection gate linesSGS (n-sel) are set in a floating state. Furthermore, each word line WLin the unselected block MB (n-sel) is set in a floating state.

Then, at time t31, the source line SL is boosted to a voltage Vera.Subsequently, at time t32, the selected drain-side selection gate lineSGD (sel) and the selected source-side selection gate line SGS (sel) areboosted to a voltage Verasg. The voltage Vera is on the order of 20V.The voltage Verasg is on the order of 15V.

Then, at time t33, the source line SL is dropped to the ground voltageVss. Subsequently, at time t34, the selected drain-side selection gateline SGD (sel) and the selected source-side selection gate line SGS(sel) are dropped to the ground voltage Vss.

Through this operation, GIDL (Gate Induced Drain Leak) current isproduced near the gates of the source-side selection transistors SSTr,and the generated holes flow into the memory columnar semiconductorlayers 35. As a result, the potential of the source line SL istransferred to the memory columnar semiconductor layers 35. On the otherhand, electrons flow toward the semiconductor substrate Ba.Consequently, due to the potential difference between the memorycolumnar semiconductor layer 35 and the first to fourth word-lineconductive layers 32a to 32d (e.g., set at 0V), the electrons areextracted from the electric charge storage layer 34b included in thememory transistors MTr1 to MTr4. That is, the erase operation isperformed.

Referring now to FIG. 9, an operation to be performed before and afterthe above-mentioned read operation will be described below. Theoperation illustrated in FIG. 9 is performed by the control signalgeneration unit 16. FIG. 9 is a flowchart illustrating an operation tobe performed before and after the read operation of the non-volatilesemiconductor storage device 100 of the first embodiment.

As illustrated in FIG. 9, pre-programming (pre-writing) is firstperformed on the unselected drain-side selection transistor SDTr (n-sel)that is connected to an unselected memory string MS (n-sel) (step S101).The pre-programming is performed by accumulating electric charges in anelectric charge storage layer 46b of the drain-side selection transistorlayer 40. This pre-programming increases the threshold voltage of thedrain-side selection transistor SDTr.

Then, data is read from the memory transistors MTr1 to MTr4 in theselected memory string MS (sel) (step S102).

Subsequently, the pre-programming of the unselected drain-side selectiontransistor SDTr (n-sel) connected to the unselected memory string MS(n-sel) is erased (step S103). The pre-programming erase is performed bydischarging electric charges from the electric charge storage layer 46bof the drain-side selection transistor layer 40. This pre-programmingerase decreases the threshold voltage of the drain-side selectiontransistor SDTr.

The above-mentioned pre-programming at step S101 is performed onunselected drain-side selection transistors SDTr (n-sel) that areconnected to unselected memory strings MS (n-sel) in an unselectedmemory block MB (n-sel), as illustrated in “Case 1” of FIG. 10. Thepre-programming is also performed on unselected drain-side selectiontransistors SDTr (n-sel) that are connected to unselected memory stringsMS (n-sel) in a selected memory block MB (sel).

Alternatively, as illustrated in “Case 2” of FIG. 11, theabove-mentioned pre-programming at step S101 is only performed onunselected drain-side selection transistors SDTr (n-sel) that areconnected to unselected memory strings MS (n-sel) in a selected memoryblock MB (sel).

In addition, as illustrated in “Case 3” of FIG. 12, the above-mentionedpre-programming at step S101 is only performed on unselected drain-sideselection transistors SDTr (n-sel) in an unselected memory block MB(n-sel).

Referring now to FIG. 13, the pre-programming operation (step S101) willbe described below. The operation illustrated in FIG. 13 is performed bythe control signal generation unit 16. FIG. 13 is a timing chartillustrating the pre-programming operation.

In this case, one of the drain-side selection gate lines SGD that issubject to the pre-programming operation is hereinafter denoted by a“target drain-side selection gate line SGD (tar)”. One of the drain-sideselection gate lines SGD that is not subject to the pre-programmingoperation is denoted by a “non-target drain-side selection gate line SGD(n-tar)”. In addition, one of the source-side selection gate lines SGSthat is subject to the pre-programming operation is denoted by a “targetsource-side selection gate line SGS (tar)”. One of the source-sideselection gate lines SGS that is not subject to the pre-programmingoperation is denoted by a “non-target source-side selection gate lineSGS (n-tar)”.

In writing data to drain-side selection transistors SDTr, unlike theword lines WL1 to WL4, data cannot be selectively written to a pluralityof drain-side selection transistors SDTr that are connected to aselected drain-side selection gate line SGD (sel). Thus, “0” data iscollectively written to all of the drain-side selection transistorsSDTr. As such, all of the bit lines BL are set at the ground voltageVss.

As illustrated in FIG. 13, a bit line BL, a source line SL, a word lineWL, a target drain-side selection gate line SGD (tar), a non-targetdrain-side selection gate line SGD (n-tar), and a source-side selectiongate line SGS are initially set at the ground voltage Vss. Then, at timet41, the target drain-side selection gate line SGD (tar) is boosted tothe voltage Vdd. Then, at time t42, the target drain-side selection gateline SGD (tar) is boosted to the voltage Vpass. Subsequently, at timet43, the target drain-side selection gate line SGD (tar) is boosted tothe voltage Vpgm. Thereafter, at time t44, the target drain-sideselection gate line SGD (tar) is dropped to the ground voltage Vss.Meanwhile, the above-mentioned operation is restated as follows: thetarget drain-side selection gate line SGD (tar) is boosted in astep-like manner.

Through this operation, due to the potential difference between thedrain-side columnar semiconductor layer 47 and the drain-side conductivelayer 42, electric charges are accumulated in the electric chargestorage layer 46b. That is, the pre-programming is performed.

Referring now to FIG. 14, the pre-programming erase operation (stepS103) will be described below. The operation illustrated in FIG. 14 isperformed by the control signal generation unit 16. FIG. 14 is a timingchart illustrating the pre-programming erase operation.

As illustrated in FIG. 14, the source line SL, the target source-sideselection gate line SGS (tar), the target drain-side selection gate lineSGD (tar), and the non-target drain-side selection gate line SGD (n-tar)are initially set at the ground voltage Vss. The word lines WL are setin a floating state. Each word line WL and non-target source-sideselection gate line SGS (n-tar) in an unselected block MB (n-sel) areset in a floating state.

Firstly, at time t51, the source line SL is boosted to the voltage Vera.Then, at time t52, the target source-side selection gate line SGS (tar),the target drain-side selection gate line SGD (tar), and the non-targetdrain-side selection gate line SGD (n-tar) are boosted to the voltageVerasg.

Subsequently, at time t53, the target drain-side selection gate line SGD(tar) is dropped to the ground voltage Vss. Then, at time t54, thesource line SL, the target source-side selection gate line SGS (tar),and the non-target drain-side selection gate line SGD (n-tar) aredropped to the ground voltage Vss.

Through this operation, GIDL (Gate Induced Drain Leak) current isproduced near the gates of the source-side selection transistors SSTr,and the generated holes flow through the memory columnar semiconductorlayers 35 into the drain-side columnar semiconductor layers 47. As aresult, the potential of the source line SL is transferred to thedrain-side columnar semiconductor layers 47. On the other hand,electrons flow toward the semiconductor substrate Ba. Consequently, thedrain-side columnar semiconductor layers 47 is boosted by the GIDLcurrent. Then, due to the potential difference between the drain-sidecolumnar semiconductor layers 47 and the drain-side selection gate linesSGD (e.g., set at 0V), the electrons are deleted in the electric chargestorage layers 46b included in the drain-side selection transistorsSDTr. That is, the pre-programming erase operation is performed.

Advantages of Non-Volatile Semiconductor Storage Device 100 in FirstEmbodiment

Advantages of the non-volatile semiconductor storage device 100 of thefirst embodiment will now be described below. As can be seen from theabove lamination structure, the non-volatile semiconductor storagedevice 100 according to the first embodiment may achieve highintegration.

In addition, as described in the above manufacturing process of thenon-volatile semiconductor storage device 100, each layer correspondingto respective memory transistors MTr, source-side selection transistorsSSTr, and drain-side selection transistors SDTr may be manufactured in acertain number of lithography steps, irrespective of the number oflaminated layers. That is, the non-volatile semiconductor storage device100 may be manufactured at a lower cost.

In addition, the non-volatile semiconductor storage device 100 isconfigured to be able to control the threshold voltages of thedrain-side selection transistors SDTr. Accordingly, prior to readingdata, the non-volatile semiconductor storage device 100 may control thethreshold voltage to be a high value for an unselected drain-sideselection transistor SDTr (n-sel) connected to an unselected memorystring MS (n-sel). Therefore, when reading data, the non-volatilesemiconductor storage device 100 may suppress the leakage current thatwould flow from a bit line BL to a source line SL through an unselectedmemory string MS (n-sel). That is, the non-volatile semiconductorstorage device 100 allows for more accurate read operation.

Second Embodiment

Configuration of Non-Volatile Semiconductor Storage Device in SecondEmbodiment

Referring now to FIG. 15, a configuration of a non-volatilesemiconductor storage device according to a second embodiment will bedescribed below. FIG. 15 is a cross-sectional view of one memory blockMBa according to the second embodiment. Note that the same referencenumerals represent the same components as the first embodiment, anddescription thereof will be omitted in the second embodiment.

The non-volatile semiconductor storage device according to the secondembodiment has memory blocks MBa different from the first embodiment.

Each memory block MBa has a source-side selection transistor layer 20Aand a drain-side selection transistor layer 40A that are different fromthe first embodiment.

The source-side selection transistor layer 20A has block insulationlayers 26a, electric charge storage layers 26b, and tunnel insulationlayers 26c, instead of the source-side gate insulation layers 26. Theblock insulation layers 26a are formed with a certain thickness on thesidewalls of the source-side holes 25. The electric charge storagelayers 26b are formed with a certain thickness on the sidewalls of theblock insulation layers 26a. The tunnel insulation layers 26c are formedwith a certain thickness on the sidewalls of the electric charge storagelayers 26b. The block insulation layers 26a and the tunnel insulationlayers 26c are composed of, e.g., silicon oxide (SiO₂). The electriccharge storage layers 26b are composed of, e.g., silicon nitride (SiN).

The drain-side selection transistor layer 40A has drain-side gateinsulation layers 46, instead of the block insulation layers 46a, theelectric charge storage layers 46b, and the tunnel insulation layers46c. The drain-side gate insulation layers 46 are formed with a certainthickness on the sidewalls of the drain-side holes 45. The drain-sidegate insulation layers 46 are composed of, e.g., silicon oxide (SiO₂).

Operation of Non-Volatile Semiconductor Storage Device in SecondEmbodiment

Referring now to FIG. 16, an operation to be performed before and afterthe read operation according to the second embodiment will be describedbelow. The operation illustrated in FIG. 16 is performed by the controlsignal generation unit 16. FIG. 16 is a flowchart illustrating anoperation to be performed before and after the read operation of thenon-volatile semiconductor storage device according to the secondembodiment.

As illustrated in FIG. 16, pre-programming (pre-writing) is firstperformed on an unselected source-side selection transistor SSTr (n-sel)that is connected to an unselected memory string MS (n-sel) (step S201).The pre-programming is performed by accumulating electric charges in anelectric charge storage layer 26b of the source-side selectiontransistor layer 20A. The pre-programming increases the thresholdvoltage of the unselected source-side selection transistor SSTr (n-sel).

Then, data is read from the memory transistors MTr1 to MTr4 in theselected memory string (sel) (step S202).

Subsequently, the pre-programming of the unselected source-sideselection transistor SSTr (n-sel) connected to the unselected memorystring (n-sel) is erased (step S203). The pre-programming erase isperformed by discharging electric charges from the electric chargestorage layer 26b of the source-side selection transistor layer 20. Thispre-programming erase decreases the threshold voltage of the unselectedsource-side selection transistor SSTr (n-sel).

The above-mentioned pre-programming at step S201 is performed onunselected drain-side selection transistors SDTr (n-sel) that areconnected to unselected memory strings MS (n-sel) in an unselectedmemory block MB (n-sel), as illustrated in “Case 4” of FIG. 17. Thepre-programming is also performed on unselected drain-side selectiontransistors SDTr (n-sel) that are connected to unselected memory stringsMS (n-sel) in a selected memory block MB (sel).

Alternatively, as illustrated in “Case 5” of FIG. 18, theabove-mentioned pre-programming at step S201 is only performed onunselected drain-side selection transistors SDTr (n-sel) that areconnected to unselected memory strings MS (n-sel) in a selected memoryblock MB (sel).

In addition, as illustrated in “Case 6” of FIG. 19, the above-mentionedpre-programming at step S201 is only performed on unselected drain-sideselection transistors SDTr (n-sel) in an unselected memory block MB(n-sel).

Referring now to FIG. 20, the pre-programming operation (step S201) willbe described below. The operation illustrated in FIG. 20 is performed bythe control signal generation unit 16. FIG. 20 is a timing chartillustrating the pre-programming operation.

As illustrated in FIG. 20, all lines are initially set at the groundvoltage Vss. Firstly, at time t61, the target source-side selection gateline SGS (tar) is boosted to the voltage Vdd. Then, at time t62, thetarget source-side selection gate line SGS (tar) is boosted to thevoltage Vpass. Subsequently, at time t63, the target source-sideselection gate line SGS (tar) is boosted to the voltage Vpgm.Thereafter, at time t64, the target source-side selection gate line SGS(tar) is dropped to the ground voltage Vss. Note that theabove-mentioned operation is restated as follows: the target source-sideselection gate line SGS (tar) is boosted in a step-like manner.

Through this operation, due to the potential difference between thesource-side columnar semiconductor layers 27 and the source-sideconductive layers 22, electric charges are accumulated in the electriccharge storage layers 26b. That is, the pre-programming is performed.

Referring now to FIG. 21, the pre-programming erase operation (stepS203) will be described below. The operation illustrated in FIG. 21 isperformed by the control signal generation unit 16. FIG. 21 is a timingchart illustrating the pre-programming erase operation.

As illustrated in FIG. 21, the source line SL, the target source-sideselection gate line SGS (tar), the non-target source-side selection gateline SGS (n-tar), and the target drain-side selection gate line SGD(tar) are initially set at the ground voltage Vss. The word line WL isset in a floating state. The non-target drain-side selection gate lineSGD (n-tar) is set in a floating state.

Then, at time t71, the source line SL is boosted to the voltage Vera.Subsequently, at time t72, the target drain-side selection gate line SGD(tar), the non-target source-side selection gate line SGS (n-tar), andthe target source-side selection gate line SGS (tar) are boosted to thevoltage Verasg.

Then, at time t73, the target source-side selection gate line SGS (tar)is dropped to the ground voltage Vss. Subsequently, at time t74, thesource line SL, the non-target source-side selection gate line SGS(n-tar), and the target drain-side selection gate line SGD (tar) aredropped to the ground voltage Vss.

Through this operation, GIDL (Gate Induced Drain Leak) current isproduced near the gates of the source-side selection transistors SSTr,and the generated holes flow into the source-side columnar semiconductorlayers 27. As a result, the potential of the source line SL istransferred to the source-side columnar semiconductor layers 27. On theother hand, electrons flow toward the semiconductor substrate Ba.Consequently, the source-side columnar semiconductor layers 27 isboosted by the GIDL current. Then, due to the potential differencebetween the source-side columnar semiconductor layers 27 and thesource-side selection gate lines SGS (e.g., set at 0V), the electronsare deleted in the electric charge storage layers 26b included in thesource-side selection transistors SSTr. That is, the pre-programmingerase operation is performed.

Advantages of Non-Volatile Semiconductor Storage Device in SecondEmbodiment

Advantages of the non-volatile semiconductor storage device according tothe second embodiment will now be described below. As can be seen fromthe above, the non-volatile semiconductor storage device according tothe second embodiment is configured to be able to control the thresholdvoltages of the source-side selection transistors SSTr. Accordingly,prior to reading data, the non-volatile semiconductor storage device maycontrol the threshold voltage to be a high value for an unselectedsource-side selection transistor SSTr (n-sel) connected to an unselectedmemory string MS (n-sel). Therefore, the non-volatile semiconductorstorage device may suppress the leakage current that would flow from abit line BL to a source line SL through an unselected memory string MS(n-sel). That is, as in the first embodiment, the non-volatilesemiconductor storage device according to the second embodiment allowsfor more accurate read operation.

Third Embodiment

Configuration of Non-Volatile Semiconductor Storage Device in ThirdEmbodiment

Referring now to FIG. 22, a configuration of a non-volatilesemiconductor storage device according to a third embodiment will bedescribed below. FIG. 22 is a cross-sectional view of one memory blockMBb according to the third embodiment. Note that the same referencenumerals represent the same components as the first and secondembodiments, and description thereof will be omitted in the thirdembodiment.

As illustrated in FIG. 22, the non-volatile semiconductor storage deviceof the third embodiment has memory blocks MBb different from the firstembodiment.

Each memory block MBb has the source-side selection transistor layer20A, the memory transistor layer 30, and the drain-side selectiontransistor layer 40 as described in the first and second embodiments.

Operation of Non-Volatile Semiconductor Storage Device in ThirdEmbodiment

An operation of the non-volatile semiconductor storage device of thethird embodiment will now be described below. The control signalgeneration unit 16 according to the third embodiment performs operationsas illustrated in FIG. 9 according to the first embodiment (step S101 to5103) and in FIG. 16 according to the second embodiment (step S201 toS203).

Advantages of Non-Volatile Semiconductor Storage Device in ThirdEmbodiment

Advantages of the non-volatile semiconductor storage device according tothe third embodiment will be described below. The non-volatilesemiconductor storage device of the third embodiment has thecharacteristics according to the first and second embodiments.Accordingly, the non-volatile semiconductor storage device of the thirdembodiment has the same advantages as the first and second embodiments.

Fourth Embodiment

Configuration of Non-Volatile Semiconductor Storage Device in FourthEmbodiment

Referring now to FIGS. 23 to 25, a configuration of a non-volatilesemiconductor storage device according to a fourth embodiment will bedescribed below. FIG. 23 is a circuit diagram of memory blocks MBc inthe non-volatile semiconductor storage device of the fourth embodiment.FIG. 24 is a schematic perspective view of one memory block MBc. FIG. 25is an enlarged cross-sectional view illustrating a part of FIG. 24. Notethat the same reference numerals represent the same components as thefirst to third embodiments, and description thereof will be omitted inthe fourth embodiment.

As illustrated in FIG. 23, each memory block MBc comprises a pluralityof memory strings MSb, source-side selection transistors SSTrb, anddrain-side selection transistors SDTrb. Each memory string MSb includesmemory transistors MTrb1 to MTrb8 connected in series and a back gatetransistor BTr. Each back gate transistor BTr is connected between amemory transistor MTrb4 and a memory transistor MTrb5. Each drain-sideselection transistor SDTrb is connected to one end (a memory transistorMTrb8) of a memory string MSb. Each source-side selection transistorSSTrb is connected to the other end (a memory transistor MTrb1) of amemory string MSb.

As illustrated in FIG. 23, in each memory block MBc, the control gatesof the memory transistors MTrb1 arranged in the row direction arecommonly connected to a word line WLb1. Similarly, the control gates ofthe memory transistors MTrb2 to MTrb8 arranged in the row direction arecommonly connected to respective word lines WLb2 to WLb8. In addition,the control gates of the back gate transistors BTr arranged in a matrixform in the row and column directions are commonly connected to a backgate line BG.

As illustrated in FIG. 23, in each memory block MBc, the control gatesof the respective drain-side selection transistors SDTrb arranged in thecolumn direction are commonly connected to a drain-side selection gateline SGDb. Each drain-side selection gate line SGDb is formed to extendin the row direction across a plurality of memory blocks MBb. Inaddition, the other ends of the drain-side selection transistors SDTrbarranged in the row direction are commonly connected to a bit line BLb.Each bit line BLb is formed to extend in the column direction across aplurality of memory blocks MBb.

As illustrated in FIG. 23, in each memory block MBc, the control gatesof the respective source-side selection transistors SSTrb arranged inthe column direction are commonly connected to a source-side selectiongate line SGSb. Each source-side selection gate line SGSb is formed toextend in the row direction across a plurality of memory blocks MBc. Inaddition, the other ends of the source-side selection transistors SSTrbarranged in the row direction are commonly connected to a source lineSLb. The neighboring source-side selection transistors SSTrb in thecolumn direction are connected to a common source line SLb. Each sourceline SLb is formed to extend in the row direction across a plurality ofmemory blocks MBc.

The circuit configuration of the memory blocks MBc as described above isachieved by the lamination structure illustrated in FIGS. 24 and 25.Each memory block MBc has a back gate transistor layer 20B, a memorytransistor layer 30B, and a selection transistor layer 40B that aresequentially laminated on a semiconductor substrate Baa. The back gatetransistor layer 20B functions as back gate transistors BTr. The memorytransistor layer 30B functions as memory strings MSb (memory transistorsMTrb1 to MTrb8). The selection transistor layer 40B functions assource-side selection transistors SSTrb and drain-side selectiontransistors SDTrb.

As illustrated in FIGS. 24 and 25, the back gate transistor layer 20Bhas a back gate conductive layer 21B. The back gate conductive layer 21Bis formed over a certain region so as to expand in the row and columndirections. The back gate conductive layer 21B is separated for eachmemory block MBc.

Each back gate conductive layer 21B is composed of, e.g., polysilicon(p-Si).

As illustrated in FIG. 25, the back gate transistor layer 20B also has aback gate hole 22B that is formed to dig into the back gate conductivelayer 21B. Each back gate hole 22B is formed to extend in the columndirection. The back gate holes 22B are formed in a matrix form in therow and column directions.

Furthermore, as illustrated in FIG. 25, the back gate transistor layer20B has a block insulation layer 23Ba, an electric charge storage layer23Bb, a tunnel insulation layer 23Bc, and a bottom semiconductor layer24B within each back gate hole 22B. Each block insulation layer 23Ba isformed with a certain thickness on the sidewall of a back gate hole 22B.Each electric charge storage layer 23Bb is formed with a certainthickness on the sidewall of a block insulation layer 23Ba. Each tunnelinsulation layer 23Bc is formed with a certain thickness on the sidewallof an electric charge storage layer 23Bb. Each bottom semiconductorlayer 24B is formed to fill up a back gate hole 22B. Each bottomsemiconductor layer 24B is formed to extend in the column direction.

The block insulation layers 23Ba and the tunnel insulation layers 23Bcare composed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 23Bb are composed of, e.g., silicon nitride (SiN). The bottomsemiconductor layers 24B are composed of, e.g., polysilicon (p-Si).

In the configuration of the back gate transistor layer 20B as mentionedabove, each back gate conductive layer 21B functions as the control gateof a back gate transistor BTr. In addition, each back gate conductivelayer 21B functions as a part of a back gate line BG.

As illustrated in FIGS. 24 and 25, the memory transistor layer 30B hasword-line conductive layers 31Ba to 31Bh. The word-line conductivelayers 31Ba to 31Bh are formed to extend in the row direction. Theword-line conductive layers 31Ba to 31Bh are insulated and isolated fromeach other via interlayer insulation layers (not illustrated). Theword-line conductive layers 31Ba to 31Bh are separated for each memoryblock MBc. The word-line conductive layer 31Ba and the word-lineconductive layer 31Bb are formed on the first (bottom) layer. Theword-line conductive layer 31Bc and the word-line conductive layer 31Bdare formed on the second layer. The word-line conductive layer 31Be andthe word-line conductive layer 31Bf are formed on the third layer. Theword-line conductive layer 31Bg and the word-line conductive layer 31Bhare formed on the fourth (top) layer.

The word-line conductive layers 31Ba to 31Bh are composed of, e.g.,polysilicon (p-Si).

As illustrated in FIG. 25, the memory transistor layer 30B also has amemory hole 32Ba that is formed to penetrate the word-line conductivelayers 31Ba, 31Bc, 31Be, and 31Bg, and a memory hole 32Bb that is formedto penetrate the word-line conductive layers 31Bb, 31Bd, 31Bf, and 31Bh.The memory holes 32Ba and 32Bb are formed in a matrix form in the rowand column directions. The memory holes 32Ba and 32Bb are formed tomatch opposite ends in the column direction of the respective back gateholes 22B.

Furthermore, as illustrated in FIG. 25, the memory transistor layer 30Bhas a block insulation layer 33Ba, an electric charge storage layer33Bb, a tunnel insulation layer 33Bc, and memory columnar semiconductorlayers 34Ba and 34Bb within respective memory holes 32Ba and 32Bb. Eachblock insulation layer 33Ba is formed with a certain thickness on thesidewall of a memory hole 32B. Each electric charge storage layer 33Bbis formed with a certain thickness on the sidewall of a block insulationlayer 33Ba. Each tunnel insulation layer 33Bc is formed with a certainthickness on the sidewall of an electric charge storage layer 33Bb. Thememory columnar semiconductor layers 34Ba and 34Bb are formed to fill uprespective memory holes 32Ba and 32Bb. Each of the memory columnarsemiconductor layers 34Ba and 34Bb is formed in a columnar shapeextending in the lamination direction. The memory columnar semiconductorlayers 34Ba and 34Bb are formed in contact with the top surface of abottom semiconductor layer 24B at opposite ends in the column direction.That is, each semiconductor layer included in a memory string MSbincludes a pair of memory columnar semiconductor layers 34Ba and 34Bb(columnar portions) and a bottom semiconductor layer 24B (a joiningportion) that is formed to join the bottom ends of the memory columnarsemiconductor layers 34Ba and 34Bb. Each semiconductor layer included ina memory string MSb is formed in a U-shape as viewed from the rowdirection.

The block insulation layers 33Ba and the tunnel insulation layers 33Bcare composed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 33Bb are composed of, e.g., silicon nitride (SiN). The memorycolumnar semiconductor layers 34B are composed of, e.g., polysilicon(p-Si).

In the configuration of the memory transistor layer 30B as mentionedabove, the word-line conductive layers 31Ba to 31Bh function as thecontrol gates of the memory transistors MTrb1 to MTrb8. In addition, theword-line conductive layers 31Ba to 31Bh function as parts of the wordlines WLb1 to WLb8.

As illustrated in FIGS. 24 and 25, the selection transistor layer 40Bhas a source-side conductive layer 41B and a drain-side conductive layer42B. Each source-side conductive layer 41B and drain-side conductivelayer 42B are formed to extend in the row direction. Each source-sideconductive layer 41B is formed above the top word-line conductive layer31Bg. Each drain-side conductive layer 42B is formed above the topword-line conductive layer 31Bh.

The source-side conductive layers 41B and the drain-side conductivelayers 42B are composed of, e.g., polysilicon (p-Si).

As illustrated in FIG. 25, the selection transistor layer 40B also has asource-side hole 43B that is formed to penetrate a source-sideconductive layer 41B, and a drain-side hole 44B that is formed topenetrate a drain-side conductive layer 42B. Each source-side hole 43Bis formed at a position matching a respective memory hole 32Ba. Eachdrain-side hole 44B is formed at a position matching respective a memoryhole 32Bb.

Furthermore, as illustrated in FIG. 25, the selection transistor layer40B has a block insulation layer 45Ba, an electric charge storage layer45Bb, a tunnel insulation layer 45Bc, and a source-side columnarsemiconductor layer 46B within each source-side hole 43B. Each blockinsulation layer 45Ba is formed with a certain thickness on the sidewallof a source-side hole 43B. Each electric charge storage layer 45Bb isformed with a certain thickness on the sidewall of a block insulationlayer 45Ba. Each tunnel insulation layer 45Bc is formed with a certainthickness on the sidewall of an electric charge storage layer 45Bb. Eachsource-side columnar semiconductor layer 46B is formed to fill up asource-side hole 43B. The source-side columnar semiconductor layers 46Bare formed in a matrix form in the row and column directions. Eachsource-side columnar semiconductor layer 46B is formed in a columnarshape extending in the lamination direction. Each source-side columnarsemiconductor layer 46B is formed in contact with the top surface of thecorresponding memory columnar semiconductor layer 34Ba.

The block insulation layers 45Ba and the tunnel insulation layers 45Bcare composed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 45Bb are composed of, e.g., silicon nitride (SiN). Thesource-side columnar semiconductor layers 46B are composed of, e.g.,polysilicon (p-Si).

Furthermore, as illustrated in FIG. 25, the selection transistor layer40B has a block insulation layer 47Ba, an electric charge storage layer47Bb, a tunnel insulation layer 47Bc, and a drain-side columnarsemiconductor layer 48B within each drain-side hole 44B. Each blockinsulation layer 47Ba is formed with a certain thickness on the sidewallof a drain-side hole 44B. Each electric charge storage layer 47Bb isformed with a certain thickness on the sidewall of a block insulationlayer 47Ba. Each tunnel insulation layer 47Bc is formed with a certainthickness on the sidewall of an electric charge storage layer 47Bb. Eachdrain-side columnar semiconductor layer 48B is formed to fill up adrain-side hole 44B. The drain-side columnar semiconductor layers 48Bare formed in a matrix form in the row and column directions. Eachdrain-side columnar semiconductor layer 48B is formed in a columnarshape extending in the lamination direction. Each drain-side columnarsemiconductor layer 48B is formed in contact with the top surface of thecorresponding memory columnar semiconductor layer 34Bb.

The block insulation layers 47Ba and the tunnel insulation layers 47Bcare composed of, e.g., silicon oxide (SiO₂). The electric charge storagelayers 47Bb are composed of, e.g., silicon nitride (SiN). The drain-sidecolumnar semiconductor layers 48B are composed of, e.g., polysilicon(p-Si).

In the configuration of the selection transistor layer 40B as mentionedabove, each source-side conductive layer 41B functions as the controlgate of a source-side selection transistor SSTrb. In addition, eachsource-side conductive layer 41B functions as a part of a source-sideselection gate line SGSb. Each drain-side conductive layer 42B functionsas the control gate of a drain-side selection transistor SDTrb. Eachdrain-side conductive layer 42B also functions as a part of a drain-sideselection gate line SGDb.

In addition, as illustrated in FIG. 24, a source-line conductive layer51B is formed on the top surfaces of the source-side columnarsemiconductor layers 46B aligned in the row direction. Each source-lineconductive layer 51B is formed to extend in the row direction. Eachsource-line conductive layer 51B functions as a source line SLb. Inaddition, bit-line conductive layers 52B are formed on the top surfacesof the drain-side columnar semiconductor layers 48B aligned in the rowdirection. Each bit-line conductive layer 52B is formed to extend in thecolumn direction. Each bit-line conductive layer 52B functions as a bitline BLb.

Operation of Non-Volatile Semiconductor Device in Fourth Embodiment

An operation of the non-volatile semiconductor device according to thefourth embodiment will now be described below. As in the thirdembodiment, prior to a read operation, the control signal generationunit 16 according to the fourth embodiment performs pre-programming onthe control gates of an unselected drain-side selection transistor SDTrb(n-sel) and an unselected source-side selection transistor SSTrb (n-sel)that are connected to an unselected memory string MSb. As a result, itincreases the threshold voltages of these control gates.

In addition, as in the third embodiment, after the read operation, thecontrol signal generation unit 16 of the fourth embodiment erases thepre-programming of the control gates of the unselected drain-sideselection transistor SDTrb (n-sel) and the unselected source-sideselection transistor SSTrb (n-sel). As a result, it decreases thethreshold voltages of these control gates.

Advantages of Non-Volatile Semiconductor Device in Fourth Embodiment

Advantages of the non-volatile semiconductor device according to thefourth embodiment will be described below. The non-volatilesemiconductor storage device of the fourth embodiment operates in thesame way as described in the third embodiment. Accordingly, thenon-volatile semiconductor storage device of the fourth embodiment hasthe same advantages as the third embodiment.

Other Embodiments

While embodiments of the non-volatile semiconductor storage device havebeen described, the present invention is not intended to be limited tothe disclosed embodiments and various other changes, additions,substitutions or the like may be made thereto without departing from thespirit of the invention.

For example, the non-volatile semiconductor storage device of the fourthembodiment may be configured to perform pre-programming only onunselected drain-side selection transistors SDTrb (n-sel) that areconnected to a selected memory string MSb (sel). The non-volatilesemiconductor storage device of the fourth embodiment may also beconfigured to perform pre-programming only on unselected source-sideselection transistors SSTrb (n-sel) that are connected to a selectedmemory string MS (sel).

What is claimed is:
 1. A non-volatile semiconductor storage devicecomprising: a plurality of memory strings, each having a plurality ofelectrically rewritable memory cells connected in series; and aplurality of first selection transistors connected to one ends of therespective memory strings, each of the memory strings comprising: afirst semiconductor layer including a columnar portion extending in adirection perpendicular to a substrate; a first electric charge storagelayer formed to surround a side surface of the columnar portion; and afirst conductive layer formed to surround a side surface of the columnarportion as well as the first electric charge storage layer, the firstconductive layer functioning as a control electrode of a respective oneof the memory cells, each of the first selection transistors comprising:a second semiconductor layer extending upward from a top surface of thecolumnar portion; a second electric charge storage layer formed tosurround a side surface of the second semiconductor layer; and a secondconductive layer formed to surround a side surface of the secondsemiconductor layer as well as the second electric charge storage layer,the second conductive layer functioning as a control electrode of arespective one of the first selection transistors, the non-volatilesemiconductor storage device further comprising a control circuitconfigured to cause, prior to reading data from a selected one of thememory strings, electric charges to be accumulated in the secondelectric charge storage layer of one of the first selection transistorsconnected to an unselected one of the memory strings.
 2. Thenon-volatile semiconductor storage device according to claim 1, whereina plurality of memory blocks each includes a plurality of the memorystrings arranged in a matrix form, and prior to reading data from aselected one of the memory strings in a selected one of the memoryblocks, the control circuit causes electric charges to be accumulated inthe second electric charge storage layer of one of the first selectiontransistors connected to an unselected one of the memory strings in theselected memory block.
 3. The non-volatile semiconductor storage deviceaccording to claim 1, wherein a plurality of memory blocks each includesa plurality of the memory strings arranged in a matrix form, and priorto reading data from a selected one of the memory strings in a selectedone of the memory blocks, the control circuit causes electric charges tobe accumulated in the second electric charge storage layers of the firstselection transistors connected to the memory strings in an unselectedone of the memory blocks.
 4. The non-volatile semiconductor storagedevice according to claim 1, wherein a plurality of memory blocks eachincludes a plurality of the memory strings arranged in a matrix form,and prior to reading data from a selected one of the memory strings in aselected one of the memory blocks, the control circuit causes electriccharges to be accumulated in the second electric charge storage layer ofone of the first selection transistors connected to an unselected one ofthe memory strings in the selected memory block, and also causeselectric charges to be accumulated in the second electric charge storagelayers of the first selection transistors connected to the memorystrings in an unselected one of the memory blocks.
 5. The non-volatilesemiconductor storage device according to claim 1, wherein after readingdata from a selected one of the memory strings, the control circuitcauses electric charges to be discharged from the second electric chargestorage layer of one of the first selection transistors connected to anunselected one of the memory strings.
 6. The non-volatile semiconductorstorage device according to claim 5, wherein the control circuit isconfigured to generate a GIDL current near a gate of one of the firstselection transistors connected to an unselected one of the memorystrings to boost a voltage at the second semiconductor layer to a firstvoltage by the GIDL current, thereby discharging electric charges storedin the second electric charge storage layer.
 7. The non-volatilesemiconductor storage device according to claim 1, wherein the controlcircuit causes electric charges to be accumulated in the second electriccharge storage layer by boosting in a step-like manner to be applied toa gate of one of the first selection transistors connected to anunselected one of the memory strings.
 8. The non-volatile semiconductorstorage device according to claim 1, comprising: a plurality of secondselection transistors connected to the other ends of the memory strings,wherein each of the second selection transistors comprises: a thirdsemiconductor layer extending downward from a bottom surface of thefirst semiconductor layer; a third electric charge storage layer formedto surround a side surface of the third semiconductor layer; and a thirdconductive layer formed to surround a side surface of the thirdsemiconductor layer as well as the third electric charge storage layer,the third conductive layer functioning as a control electrode of arespective one of the second selection transistors, and prior to readingdata from a selected one of the memory strings, the control circuitcauses electric charges to be accumulated in the third electric chargestorage layer of one of the second selection transistors connected to anunselected one of the memory strings.
 9. The non-volatile semiconductorstorage device according to claim 8, wherein a plurality of memoryblocks each includes a plurality of the memory strings arranged in amatrix form, and prior to reading data from a selected one of the memorystrings in a selected one of the memory blocks, the control circuitcauses electric charges to be accumulated in the third electric chargestorage layer of one of the second selection transistors connected to anunselected one of the memory strings in the selected memory block. 10.The non-volatile semiconductor storage device according to claim 8,wherein a plurality of memory blocks each includes a plurality of thememory strings arranged in a matrix form, and prior to reading data froma selected one of the memory strings in a selected one of the memoryblocks, the control circuit causes electric charges to be accumulated inthe third electric charge storage layers of the second selectiontransistors connected to the memory strings in an unselected one of thememory blocks.
 11. The non-volatile semiconductor storage deviceaccording to claim 8, wherein a plurality of memory blocks each includesa plurality of the memory strings arranged in a matrix form, and priorto reading data from a selected one of the memory strings in a selectedone of the memory blocks, the control circuit causes electric charges tobe accumulated in the third electric charge storage layer of one of thesecond selection transistors connected to an unselected one of thememory strings in the selected memory block, and also causes electriccharges to be accumulated in the third electric charge storage layers ofthe second selection transistors connected to the memory strings in anunselected one of the memory blocks.
 12. The non-volatile semiconductorstorage device according to claim 8, wherein after reading data from aselected one of the memory strings, the control circuit causes electriccharges to be discharged from the third electric charge storage layer ofone of the second selection transistors connected to an unselected oneof the memory strings.
 13. The non-volatile semiconductor storage deviceaccording to claim 12, wherein the control circuit is configured togenerate a GIDL current near a gate of one of the second selectiontransistors connected to an unselected one of the memory strings toboost a voltage at the third semiconductor layer to a second voltage bythe GIDL current, thereby discharging electric charges stored in thethird electric charge storage layer.
 14. The non-volatile semiconductorstorage device according to claim 8, wherein the control circuit causeselectric charges to be accumulated in the third electric charge storagelayer by boosting in a step-like manner a voltage to be applied to agate of one of the second selection transistors connected to anunselected one of the memory strings.
 15. The non-volatile semiconductorstorage device according to claim 1, wherein the first semiconductorlayer comprises a joining portion formed to join bottom ends of a pairof the columnar portions.
 16. A non-volatile semiconductor storagedevice comprising: a plurality of memory strings, each having aplurality of electrically rewritable memory cells connected in series;and a plurality of first selection transistors connected to one ends ofthe respective memory strings, each of the memory strings comprising: afirst semiconductor layer including a columnar portion extending in adirection perpendicular to a substrate; a first electric charge storagelayer formed to surround a side surface of the columnar portion; and afirst conductive layer formed to surround a side surface of the columnarportion as well as the first electric charge storage layer, the firstconductive layer functioning as a control electrode of a respective oneof the memory cells, each of the first selection transistors comprising:a second semiconductor layer extending downward from a bottom surface ofthe columnar portion; a second electric charge storage layer formed tosurround a side surface of the second semiconductor layer; and a secondconductive layer formed to surround a side surface of the secondsemiconductor layer as well as the second electric charge storage layer,the second conductive layer functioning as a control electrode of arespective one of the first selection transistors, the non-volatilesemiconductor storage device further comprising a control circuitconfigured to cause, prior to reading data from a selected one of thememory strings, electric charges to be accumulated in the secondelectric charge storage layer of one of the first selection transistorsconnected to an unselected one of the memory strings.
 17. Thenon-volatile semiconductor storage device according to claim 16, whereina plurality of memory blocks each includes a plurality of the memorystrings arranged in a matrix form, and prior to reading data from aselected one of the memory strings in a selected one of the memoryblocks, the control circuit causes electric charges to be accumulated inthe second electric charge storage layer of one of the first selectiontransistors connected to an unselected one of the memory strings in theselected memory block.
 18. The non-volatile semiconductor storage deviceaccording to claim 16, wherein a plurality of memory blocks eachincludes a plurality of the memory strings arranged in a matrix form,and prior to reading data from a selected one of the memory strings in aselected one of the memory blocks, the control circuit causes electriccharges to be accumulated in the second electric charge storage layersof the first selection transistors connected to the memory strings in anunselected one of the memory blocks.
 19. The non-volatile semiconductorstorage device according to claim 16, wherein a plurality of memoryblocks each includes a plurality of the memory strings arranged in amatrix form, and prior to reading data from a selected one of the memorystrings in a selected one of the memory blocks, the control circuitcauses electric charges to be accumulated in the second electric chargestorage layer of one of the first selection transistors connected to anunselected one of the memory strings in the selected memory block, andalso causes electric charges to be accumulated in the second electriccharge storage layers of the first selection transistors connected tothe memory strings in an unselected one of the memory blocks.
 20. Thenon-volatile semiconductor storage device according to claim 16, whereinafter reading data from a selected one of the memory strings, thecontrol circuit causes electric charges to be discharged from the secondelectric charge storage layer of one of the first selection transistorsconnected to an unselected one of the memory strings.
 21. A non-volatilesemiconductor storage device comprising: a plurality of memory stringsincluding a plurality of memory cells, the memory strings including afirst memory string and a second memory string, a first selectiontransistor coupled to one end of the first memory string and a bit line;a second selection transistor coupled to one end of the second memorystring and the bit line; a word line coupled to a gate of one of thememory cells in the first memory string and a gate of one of the memorycells in the second memory string; a first line coupled to a gate of thefirst selection transistor; a second line coupled to a gate of thesecond selection transistor; and a controller configured to perform apre-program operation and a program operation, the pre-program operationincluding a first phase and the program operation including a secondphase, the controller configured to apply a first program voltage to thefirst line, a first voltage to the second line, and a second voltage tothe word line during the first phase, and the controller configured toapply a third voltage to the first line, a fourth voltage to the secondline, and a second program voltage to the word line during the secondphase; wherein the first program voltage and the second program voltageare higher than the first voltage, the second voltage, the thirdvoltage, and the fourth voltage.
 22. The non-volatile semiconductorstorage device according to claim 21 wherein the controller isconfigured to program one of the memory cells in the program operation.23. The non-volatile semiconductor storage device according to claim 21wherein the first, second, and fourth voltages are zero voltages and thefirst program voltage is substantially same as the second programvoltage.
 24. The non-volatile semiconductor storage device according toclaim 21 wherein the program operation includes a third phase before thesecond phase; the controller further configured to apply a fifth voltageto the first line and apply a sixth voltage to the word line, the fifthvoltage being substantially same as the sixth voltage, in the thirdphase.
 25. The non-volatile semiconductor storage device according toclaim 24 wherein the fifth voltage is higher than zero voltage and lowerthan the first program voltage and the second program voltage.
 26. Thenon-volatile semiconductor storage device according to claim 21 whereinthe controller is configured to perform a pre-program erase operationincluding a fourth phase; the controller further configured to apply aseventh voltage to the first line and set the word line in a floatingstate during the fourth phase, wherein the seventh voltage is lower thanthe first program voltage and the second program voltage and the seventhvoltage is higher than the first voltage, the second voltage, the thirdvoltage, and the fourth voltage.
 27. The non-volatile semiconductorstorage device according to claim 26 wherein the controller isconfigured to perform the pre-program operation, a read operation, andthe pre-program erase operation in this order.
 28. A non-volatilesemiconductor storage device comprising: a plurality of memory stringsincluding a plurality of memory cells, the memory strings including afirst memory string and a second memory string, a first selectiontransistor coupled to one end of the first memory string and a sourceline; a second selection transistor coupled to one end of the secondmemory string and the source line; a word line electrically coupled to agate of one of the memory cells in the first memory string and a gate ofone of the memory cells in the second memory string; a first linecoupled to a gate of the first selection transistor; a second linecoupled to a gate of the second selection transistor; and a controllerconfigured to perform a pre-program operation and a program operation,the pre-program operation including a first phase and the programoperation including a second phase, the controller configured to apply afirst program voltage to the first line, a first voltage to the secondline, and a second voltage to the word line during the first phase, andthe controller configured to apply a third voltage to the first line anda fourth voltage to the second line and a second program voltage to theword line during the second phase, wherein the first program voltage andthe second program voltage are higher than the first voltage, the secondvoltage, the third voltage, and the fourth voltage.
 29. The non-volatilesemiconductor storage device according to claim 28 wherein the first,second, and fourth voltages are zero voltages and the first programvoltage is substantially same as the second program voltage.
 30. Thenon-volatile semiconductor storage device according to claim 28 whereinthe program operation includes a third phase; the controller furtherconfigured to apply a fifth voltage to the first line and apply a sixthvoltage to the word line, the fifth voltage being higher than the sixthvoltage, and the fifth voltage being higher than the third voltage, inthe third phase after the second phase.
 31. The non-volatilesemiconductor storage device according to claim 30 wherein the fifthvoltage is higher than zero voltage and lower than the first programvoltage and the second program voltage.
 32. The non-volatilesemiconductor storage device according to claim 28 wherein thecontroller is further configured to perform the pre-program operationbefore a read operation.
 33. The non-volatile semiconductor storagedevice according to claim 32 wherein the controller is furtherconfigured to perform a pre-program erase operation including a fourthphase; the controller further configured to apply a seventh voltage tothe first line and set the word line in a floating stat during thefourth phase, wherein the seventh voltage is lower than the firstprogram voltage and the second program voltage and the seventh voltageare higher than the first to fourth voltages.
 34. The non-volatilesemiconductor storage device according to claim 33 wherein thecontroller is configured to perform the pre-program operation, a readoperation, and the pre-program erase operation in this order.